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RM0008
Advanced-control timers (TIM1&TIM8)
Figure 79. Output stage of capture/compare channel (channel 1 to 3)
ETR
0
Output
OC1
‘0’
x0
1
enable
circuit
10
CNT>CCR1
OC1_DT
11
CC1P
CNT=CCR1
Output mode OC1REF
controller
Dead-time
generator
OC1N_DT
‘0’
11
10
0x
TIM1_CCER
0
1
Output
enable
circuit
OC1N
CC1NE CC1E TIM1_CCER
OC1CE OC1M[2:0]
TIM1_CCMR1
DTG[7:0]
TIM1_BDTR
CC1NE CC1E
TIM1_CCER
CC1NP MOE OSSI OSSR TIM1_BDTR
TIM1_CCER
Figure 80. Output stage of capture/compare channel (channel 4)
ETR
To the master mode
controller
0
Output
OC4
enable
1
circuit
CNT > CCR4
CC4P
CNT = CCR4
Output mode OC4 REF
controller
OC2M[2:0]
TIM1_CCMR2
TIM1_CCER
CC4E TIM1_CCER
MOE OSSI TIM1_BDTR
OIS4 TIM1_CR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
13.3.6
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
Doc ID 13902 Rev 9
271/995
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